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ltc1960 1 1960fb typical application features description dual battery charger/ selector with spi interface the ltc ? 1960 is a highly integrated battery charger and selector intended for portable products using dual smart batteries. a serial spi interface allows an external microcon - troller to control and monitor status of both batteries. a proprietary powerpath architecture supports simulta - neous charging or discharging of both batteries. typical battery run times are extended by 10%, while charging times are reduced by up to 50%. the ltc1960 automati - cally switches between power sources in less than 10s to prevent power interruption upon battery or wall adapter removal. the synchronous buck battery charger delivers 95% effi- ciency with only 0.5v dropout voltage, and prevents audible noise in all operating modes. patented input current limit - ing with 5% accuracy charges batteries in the shortest possible time without overloading the wall adapter. the ltc1960?s 5mm 7mm 38-pin qfn and 36-pin nar - row ssop packages allow implementation of a complete sbs-compliant dual battery system while consuming minimum pcb area. ltc1960 dual battery/selector system architecture applications n complete dual-battery charger/selector system n serial spi interface allows external c control and monitoring n simultaneous dual-battery discharge extends run time by typically 10% n simultaneous dual-battery charging reduces charging time by up to 50% n automatic powerpath? switching in <10s prevents power interruption n circuit breaker protects against overcurrent faults n 5% accurate adapter current limit maximizes charging rate n 95% efficient synchronous buck charger n charger has low 0.5v dropout voltage n no audible noise generation, even with ceramic capacitors n 11-bit vdac delivers 0.8% voltage accuracy n 10-bit idac delivers 5% current accuracy n v in up to 32v; v batt up to 28v n available in 5mm 7mm 38-pin qfn and 36-pin narrow ssop packages n portable computers n portable instruments l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no r sense and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5723970, 6304066, 6580258. dual vs sequential charging ltc1960 microcontroller dc in 4 system power smbus 1960 ta01 bat2 bat1 spi time (minutes) battery current (ma) 35003000 2500 2000 1500 1000 500 0 35003000 2500 2000 1500 1000 500 0 1960 ta01b 0 50 100 150 200 250 300 bat1current bat2current sequential dual bat1 current 100 minutes battery type: 10.8v li-ion (moltech ni2020)requested current = 3a requested voltage = 12.3v max charger current = 4.1a bat2current downloaded from: http:///
ltc1960 2 1960fb absolute maximum ratings voltage from dcin, scp, scn, clp, v plus , sw to gnd ................................................. ?0.3v to 32v voltage from sch1, sch2 to gnd ............. ?0.3v to 28v voltage from boost to gnd ...................... ?0.3v to 41v pgnd with respect to gnd ................................... 0.3v csp, csn, bat1, bat2 to gnd ...................... ?5v to 28v lopwr, dcdiv to gnd ............................. ?0.3v to 10v ssb, sck, mosi, miso to gnd ................... ?0.3v to 7v (note 1) 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 3625 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 v plus bat2 bat1 scn scp gdco gdci gb1o gb1i gb2o gb2i lopwr v set i th i set gnd dcdiv ssb sch2gch2 gch1 sch1 tgate boost sw dcin v cc bgate pgnd comp1 clp csp csn mosi miso sck t jmax = 125c, ja = 70c/w 13 14 15 16 top view 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 v set i th i set gnd dcdiv ssbsck misomosi gnd csn csp scpscn bat1 bat2 v plus gndsch2 gch2 gch1 sch1 tgate boost lopwrgb2i gb2o gb1i gb1o gdci gdco clp comp1 pgnd bgate v cc dcin sw 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w the exposed pad (pin 39) is gnd. must be soldered to the pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc1960cg#pbf ltc1960cg#trpbf ltc1960cg 36-lead plastic ssop 0c to 70c LTC1960CUHF#pbf LTC1960CUHF#trpbf 1960 38-lead (5mm 7mm) plastic qfn 0c to 70c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ comp1 to gnd ............................................ ?0.3v to 5v operating ambient temperature range (note 7) ............................................ 0c to 70c operating junction temperature ............ ?40c to 125c storage temperature .............................. ?65c to 150c lead temperature (soldering, 10 sec) ssop only ........................................................ 300c downloaded from: http:///
ltc1960 3 1960fb electrical characteristics symbol parameter conditions min typ max units supply and reference dcin operating range dcin selected 6 28 v i ch dcin operating current not charging (dcin selected) charging (dcin selected) 1 1.3 1.5 2 ma ma battery operating voltage range battery selected, powerpath function (note 2) 6 28 v battery drain current battery selected, not charging, v dcin = 0v 175 a v fdc v fb1 v fb2 v fscn v plus diodes forward voltage: dcin to v plus bat1 to v plus bat2 to v plus scn to v plus i vcc = 10ma i vcc = 0ma i vcc = 0ma i vcc = 0ma 0.8 0.7 0.7 0.7 v v v v uvlo undervoltage lockout threshold v plus ramping down, measured at v plus to gnd l 3 3.5 3.9 v uvhys uv lockout hysteresis v plus rising, measured at v plus to gnd 60 mv v vcc v cc regulator output voltage 5 5.2 5.4 v v ldr v cc load regulation i vcc = 0ma to 10ma 0.2 1 % switching regulatorv tol overall voltage accuracy 5v v out < 25v, (note 3) l ?0.8 ?1 0.8 1 % % i tol overall current accuracy idac value = 3ff hex v csp , v csn = 12v l ?5 ?6 5 6 % % f osc regulator switching frequency 255 300 345 khz f do regulator switching frequency in low dropout mode duty cycle 99% 20 25 khz dc max regulator maximum duty cycle 99 99.5 % i max maximum current sense threshold v ith = 2.2v 140 155 190 mv i sns ca1 input bias current v csp = v csn > 5v 150 a cmsl cai input common mode low 0 v cmsh cai input common mode high v dcin ?0.2 v v cl1 cl1 turn-on threshold 95 100 105 mv tg t r tg t f tgate transition time: tgate rise time tgate fall time c load = 3300pf, 10% to 90% c load = 3300pf, 10% to 90% 50 50 90 90 ns ns bg t r bg t f bgate transition time: bgate rise time bgate fall time c load = 3300pf, 10% to 90% c load = 3300pf, 10% to 90% 50 40 90 80 ns ns trip points v tr dcdiv/lopwr threshold v dcdiv or v lopwr falling l 1.166 1.19 1.215 v v thys dcdiv/lopwr hysteresis voltage v dcdiv or v lopwr rising 30 mv i bvt dcdiv/lopwr input bias current v dcdiv or v lopwr = 1.19v 20 200 na v tsc short-circuit comparator threshold v scp ? v scn , v cc 5v l 90 100 115 mv v fto fast powerpath turn-off threshold v dcdiv rising from v cc 6 7 7.9 v v ovsd overvoltage shutdown threshold as a percent of programmed charger voltage v set rising from 0.8v until tgate and bgate stop switching 107 % the l denotes the specifications which apply over the full operating temperature range (note 7), otherwise specifications are at t a = 25c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, unless otherwise noted. downloaded from: http:///
ltc1960 4 1960fb symbol parameter conditions min typ max units dacsi res idac resolution guaranteed monotonic above i max /16 10 bits t ip t ilow idac pulse period: normal mode low current mode 6 10 50 15 s ms v res vdac resolution guaranteed monotonic (5v < v bat < 25v) 11 bits v step vdac granularity 16 mv v off vdac offset (note 6) 0.8 v t vp vdac pulse period 7 11 16.5 s charge mux switchest onc gch1/gch2 turn-on time v gchx ? v schx > 3v, c load = 3nf 5 10 ms t onc gch1/gch2 turn-off time v gchx ? v schx < 1v, from time of v csn < v batx ? 30mv, c load = 3nf 3 7 s v con ch gate clamp voltage gch1 gch2 i load = 1a v gch1 ? v sch1 v gch2 ? v sch2 5 5 5.8 5.8 7 7 v v v coff ch gate off voltage gch1 gch2 i load = 10a v gch1 ? v sch1 v gch2 ? v sch2 ?0.8 ?0.8 ?0.4 ?0.4 0 0 v v v toc ch switch reverse turn-off voltage v csn ? v batx , 5v v batx 28v l 5 20 40 mv v fc ch switch forward regulation voltage v batx ? v csn , 5v v batx 28v l 15 35 60 mv i oc(src) i oc(snk) gch1/gch2 active regulation: max source current max sink current v gchx ? v schx = 1.5v ?2 2 a a v chmin batx voltage below which charging is inhibited (note 8) 3.5 4.7 v powerpath switchest d ly blanking period after uvlo trip switches held off 250 ms t ppb blanking period after lopwr trip switches in 3-diode mode 1 sec t onpo gb1o/gb2o/gdco turn-on time v gs < ?3v, from time of battery/dc removal, or lopwr indication l 5 10 s t offpo gb1o/gb2o/gdco turn-off time v gs > ?1v, from time of battery/dc removal, or lopwr indication l 3 7 s v pono output gate clamp voltage gb1o gb2o gdco i load = 1a highest (v bat1 or v scp ) ? v gb1o highest (v bat2 or v scp ) ? v gb2o highest (v dcin or v scp ) ? v gdco 4.75 4.75 4.75 6.25 6.25 6.25 7 7 7 v v v v poffo output gate off voltage gb1o gb2o gdco i load = ?25a highest (v bat1 or v scp ) ? v gb1o highest (v bat2 or v scp ) ? v gb2o highest (v dcin or v scp ) ? v gdco 0.18 0.18 0.18 0.25 0.25 0.25 v v v v top powerpath switch reverse turn-off voltage v scp ? v batx or v scp ? v dcin 6v v scp 28v l 5 20 60 mv v fp powerpath switch forward regulation voltage v batx ? v scp or v dcin ? v scp 6v v scp 28v l 0 25 50 mv i op(src) i op(snk) gdci/gb1i/gb2i active regulation source current sink current (note 4) ?4 75 a a electrical characteristics the l denotes the specifications which apply over the full operating temperature range (note 7), otherwise specifications are at t a = 25c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, unless otherwise noted. downloaded from: http:///
ltc1960 5 1960fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. battery voltage must be adequate to drive gates of powerpath p-channel fet switches. this does not affect charging voltage of the battery, which can be zero volts. note 3. see test circuit. note 4 . dcin, bat1, bat2 are held at 12v and gdci, gb1i, gb2i are forced to 10.5v. scp is set at 12.0v to measure source current at gdci, symbol parameter conditions min typ max units t onpi gate b1i/b2i/dci turn-on time v gs < ?3v, c load = 3nf (note 5) 300 s t offpi gate b1i/b2i/dci turn-off time v gs > ?1v, c load = 3nf (note 5) 10 s v poni input gate clamp voltage gb1i gb2i gdci i load = 1a highest (v bat1 or v scp ) ? v gb1i highest (v bat2 or v scp ) ? v gb2i highest (v dcin or v scp ) ? v gdci 4.75 4.75 4.75 6.7 6.7 6.7 7.5 7.5 7.5 v v v v poffi input gate off voltage gb1i gb2i gdci i load = 25a highest (v bat1 or v scp ) ? v gb1i highest (v bat2 or v scp ) ? v gb2i highest (v dcin or v scp ) ? v gdci 0.18 0.18 0.18 0.25 0.25 0.25 v v v logic i/oi ih /i il ssb/sck/mosi input high/low current l ?1 1 a v il ssb/mosi/sck input low voltage l 0.8 v v ih ssb/mosi/sck input high voltage l 2 v v ol miso output low voltage i ol = 1.3ma l 0.4 v i off miso output off-state leakage current v miso = 5v l 2 a spi timing (see timing diagram) t wd watch dog timer l 1.2 2.5 4.5 sec t ssh ssb high time 680 ns t cyc sck period c load = 200pf r pullup = 4.7k on miso l 2 s t sh sck high time 680 ns t sl sck low time 680 ns t ld enable lead time 200 ns t lg enable lag time 200 ns t su input data set-up time l 100 ns t h input data hold time l 100 ns t a access time (from hi-z to data active on miso) l 125 ns t dis disable time (hold time to hi-z state on miso) l 125 ns t v output data valid c l = 200pf, r pullup = 4.7k on miso l 580 ns t ho output data hold l 0 ns t ir sck/mosi/ssb rise time 0.8v to 2v 250 ns t if sck/mosi/ssb fall time 2v to 0.8v 250 ns t of miso fall time 2v to 0.4v, c l = 200pf l 400 ns electrical characteristics the l denotes the specifications which apply over the full operating temperature range (note 7), otherwise specifications are at t a = 25c. v dcin = 20v, v bat1 = 12v, v bat2 = 12v, unless otherwise noted. gb1i and gb2i. scp is set at 11.9v to measure sink current at gdci, gb1i and gb2i. note 5. extrapolated from testing with c l = 50pf. note 6. vdac offset is equal to the reference voltage, since v out = v ref (16mv ? vdac (value) /2047 + 1) note 7. the ltc1960c is guaranteed to meet specified performance from 0c to 70c and is designed, characterized and expected to meet specified performance at ?40c and 85c, but is not tested at these extended temperature limits. note 8. does not apply to low current mode. refer to ?the current dac block? in the operation section. downloaded from: http:///
ltc1960 6 1960fb typical performance characteristics charger efficiency charger start-up charger load dump charger load regulation charging current accuracy idac low current mode vs normal mode battery drain current (bat1 selected) powerpath switching powerpath autonomous switching bat1 voltage (v) 6 bat1 current (a) 30 1960 g01 12 18 24 250240 230 220 210 200 190 180 170 160 150 t a = 25c time (s) 1615 14 13 12 11 10 98 7 6 load voltage (v) 1960 g02 ?50 ?40 ?30 ?10 0 10 20 30 40 50 ?20 c load = 20f i load = 0.8a t a = 25c lopwrthreshold time (sec) ?1 load voltage (v) 0 1 2 3 1960 g03 4 1615 14 13 12 11 10 98 7 6 5 bat1removed note: light load to exaggerate switching event i out (a) 0 0 efficiency (%) 10 30 40 50 100 70 0.025 0.10 1960 g04 20 80 9060 0.50 2.5 4.0 time (sec) ?0.05 charger output (v) 0.05 0.15 0.20 0.40 1960 g05 0 0.10 0.25 0.30 0.35 1210 86 4 2 0 time (ms) ?4 ?2 bat1 voltage (v) 1412 10 86 4 2 0 1960 g06 4 2 10 12 14 16 0 6 8 v in = 20v vdac = 12.29vidac = 3000ma load current = 1a t a = 25c bat1output loadconnected load disconnected charge current (ma) 0 bat1 voltage (v) 4000 1960 g07 1000 2000 3000 12.412.3 12.2 12.1 12.0 11.9 11.8 11.7 11.6 v in = 20v vdac = 12.288vidac = 4000ma t a = 25c idac value 0 200 output current error (ma) 400 800 600 1000 1200 1960 g08 120100 8060 40 20 0 ?20?40 v dcin = 20v v bat1 = 12v r sns = 0.025 t a = 25c programmed current (ma) 0 charging current (ma) 500450 400 350 300 250 200 150 100 50 0 160 320 400 1960 g09 80 240 480 560 low current mode normalmode v in = 20v v bat1 = 12v r sns = 0.025 t a = 25c downloaded from: http:///
ltc1960 7 1960fb vdac value 250 450 output voltage error (mv) 650 1050 850 1250 1450 1960 g10 100 7550 25 0 C25C50 C75 C100 dcin = 24vt a = 25c i load = 100ma time (minutes) battery current (ma) 35003000 2500 2000 1500 1000 500 0 35003000 2500 2000 1500 1000 500 0 1960 g11 0 50 100 150 200 250 300 bat1current bat2current sequential dual bat1 current 100 minutes battery type: 10.8v li-ion (moltech ni2020)requested current = 3a requested voltage = 12.3v max charger current = 4.1a bat2current bat2 voltage bat2 current bat1current bat1voltage bat1 initial capacity = 0%bat2 initial capacity = 90% programmed charger current = 3a programmed charger voltage = 16.8v time (minutes) 0 battery voltage (v) 120 1960 g12 40 80 160 17.016.5 16.0 15.5 15.0 14.5 14.0 13.5 20 60 100 140 battery current (ma) 35003000 2500 2000 1500 1000 500 0 time (minutes) 0 battery voltage (v) 120 12.011.0 10.0 9.08.0 12.011.0 10.0 9.08.0 1960 g13 20 180 40 60 80 100 140 160 bat1 voltage bat1 voltage dual sequential bat2 voltage bat2 voltage battery type: 10.8v li-ion(moltech ni2020)load current = 3a 11 minutes time (minutes) 0 120 20 40 60 80 100 140 battery voltage (v) 1514 13 12 11 10 1514 13 12 11 10 1960 g14 bat2 voltage bat2 voltage bat1 voltage bat1 voltage battery type: 12v nimh (moltech nj1020)load: 33w 16 minutes dual sequential typical performance characteristics dual vs sequential discharge dual vs sequential discharge voltage accuracy dual vs sequential charging dual charging batteries with different charge state downloaded from: http:///
ltc1960 8 1960fb pin functions input power related scn (pin 4/pin 30): powerpath current sensing negative input. this pin should be connected directly to the bottom (output side) of the sense resistor, r sc , in series with the three powerpath switch pairs, for detecting short-circuit current events. also powers ltc1960 internal circuitry when all other sources are absent. scp (pin 5/pin 31): powerpath current sensing positive input. this pin should be connected directly to the top (switch side) of the sense resistor, r sc , in series with the three powerpath switch pairs, for detecting short-circuit current events. gdco (pin 6/pin 32): dcin output switch gate drive. together with gdci, this pin drives the gate of the p-channel switch in series with the dcin input switch.gdci (pin 7/pin 33): dcin input switch gate drive. together with gdco, this pin drives the gate of the p-channel switch connected to the dcin input.gb1o (pin 8/pin 34): bat1 output switch gate drive. together with gb1i, this pin drives the gate of the p-channel switch in series with the bat1 input switch. gb1i (pin 9/pin 35): bat1 input switch gate drive. together with gb1o, this pin drives the gate of the p-channel switch connected to the bat1 input. gb2o (pin 10/pin 36): bat2 output switch gate drive. together with gb2i, this pin drives the gate of the p-channel switch in series with the bat2 input switch. gb2i (pin 11/pin 37): bat2 input switch gate drive. together with gb2o, this pin drives the gate of the p-channel switch connected to the bat2 input. clp (pin 24/pin 13): the positive input to the supply current limiting amplifier cl1. the threshold is set at 100mv above the voltage at the dcin pin. when used to limit supply current, a filter is needed to filter out the switching noise. battery charging related v set (pin 13/pin 1): the tap point of a programmable resistor divider which provides battery voltage feedback to the charger. a capacitor from csn to v set and from v set to gnd provide necessary compensation and filtering for the voltage loop.i th (pin 14/pin 2): the control signal of the inner loop of the current mode pwm. higher i th voltage corresponds to higher charging current in normal operation. a capacitor of at least 0.1f to gnd filters out pwm ripple. typical full-scale output current is 30a. nominal voltage range for this pin is 0v to 2.4v. i set (pin 15/pin 3): a capacitor from i set to ground is required to filter higher frequency components from the delta-sigma idac. csn (pin 22/pin 11): current amplifier ca1 input. con - nect this to the common output of the charger mux switches. csp (pin 23/pin 12): current amplifier ca1 input. this pin and the csn pin measure the voltage across the sense resistor, r sns , to provide the instantaneous cur - rent signals required for both peak and average current mode operation. comp1 (pin 25/pin 14): the compensation node for the amplifier cl1. a capacitor is required from this pin to gnd if input current amplifier cl1 is used. at input adapter current limit, this node rises to 1v. by forcing comp1 low, amplifier cl1 will be defeated (no adapter current limit). comp1 can source 10a. bgate (pin 27/pin 16): drives the bottom external mosfet of the battery charger buck converter. sw (pin 30/pin 19): pwm switch node connected to source of the top external mosfet switch. used as reference for top gate driver. boost (pin 31/pin 20): supply to topside floating driver. the bootstrap capacitor is returned to this pin. voltage swing at this pin is from a diode drop below v cc to (dcin + v cc ). (g/uhf) downloaded from: http:///
ltc1960 9 1960fb tgate (pin 32/pin 21): drives the top external mosfet of the battery charger buck converter. sch1 (pin 33/pin 22), sch2 (pin 36/pin 25): charger mux n-channel switch source returns. these two pins are connected to the sources of the back-to-back switch pairs, q3/q4 and q9/q10 (see typical application on back page of data sheet), respectively. a small pull-down cur - rent source returns these nodes to 0v when the switches are turned off. gch1 (pin 34/pin 23), gch2 (pin 35/pin 24): charger mux n-channel switch gate drives. these two pins drive the gates of the back-to-back switch pairs, q3/q4 and q9/ q10, between the charger output and the two batteries. external power supply pins v plus (pin 1/pin 27): supply. the v plus pin is connected via four internal diodes to the dcin, scn, bat1, and bat2 pins. bypass this pin with a 1f to 2f capacitor. bat1 (pin 3/pin 29), bat2 (pin 2/pin 28): these two pins are the inputs from the two batteries for power to the ltc1960 and to provide voltage feedback to the bat - tery charger. lopwr (pin 12/pin 38): lopwr comparator input from scn external resistor divider to gnd. if the voltage at lopwr is lower than the lopwr comparator threshold, then system power has failed and power is autonomously switched to a higher voltage source, if available. see powerpath section of ltc1960 operation. dcdiv (pin 17/pin 5): external dc source comparator input from dcin external resistor divider to gnd. if the voltage at dcdiv is above the dcdiv comparator thresh - old, then the dc bit is set and the wall adapter power is considered to be adequate to charge the batteries. if dcdiv rises more than 1.8v above v cc , then all of the powerpath switches are latched off until all power is removed. a capacitor from dcdiv to gnd is recommended to prevent noise-induced false emergency turn-off conditions from being detected. refer to fast powerpath turn-off in the operation section and the typical application on the back page of this data sheet. dcin (pin 29/pin 18): supply. external dc power source. a 1f bypass capacitor should be connected to this pin as close as possible. no series resistance is allowed, since the adapter current limit comparator input is also this pin. internal power supply pins gnd (pin 16/pin 4, pin 10, pin 26, pin 39): ground for low power circuitry. pgnd (pin 26/pin 15): high current ground return for bgate driver. v cc (pin 28/pin 17): internal regulator output. bypass this output with at least a 2f to 4.7f capacitor. do not use this regulator output to supply more than 1ma to external circuitry. digital interface pins ssb (pin 18/pin 6): spi slave select input. active low. ttl levels. this signal is low when clocking data to/from the ltc1960. sck (pin 19/pin 7): serial spi clock. ttl levels. miso (pin 20/pin 8): spi master-in-slave-out output, open drain. serial data is transmitted from the ltc1960, when ssb is low, on the falling edge of sck. ttl levels. a 4.7k pull-up resistor is recommended. mosi (pin 21/pin 9): spi master-out-slave-in input. serial data is transmitted to the ltc1960, when ssb is low, on the rising edge of sck. ttl levels. gnd (exposed pad pin 39, uhf package only): ground. must be soldered to the pcb ground for rated thermal performance. pin functions (g/uhf) downloaded from: http:///
ltc1960 10 1960fb block diagram spi interface 11-bit ? voltage dac 10-bit ? current dac selector controller charge + C + C + C + C C C C C C 1.19v 100 100mv swb1 driver charge pump swb2 driver swdc driver csn + C on + C on dcin gch1 sch2 gch2 sch1 tgate pgnd bgate sw bat1 gnd v cc dcindcin v set v plus bat2 v cc regulator oscillator low dropdetect t on + boost bgate v cc pwm logic chgmon 400k 0.86v 0.8v + + + + q sr charge 100mv clp + chgmon 0.75v 40mv + C 15 scn gb1i gb1o gb2i gb2o gdci gdco short circuit ac_present scpscn dcdiv lopwr mosi miso sck ssb csp csn i set ca1 3k 3k 0.8v buffered i th g m = 1.4m g m = 0.4m clamp i rev i cmp i th comp1 ea 0v 11 1960 bd csp-csn 3k g m = 1.4m 24 26 27 30 32 31 13 29 16 28 1 2 3 36 35 33 34 9 8 11 10 7 6 25 14 54 17 12 21 20 1918 15 2322 cl1 ca2 C C + (ltc1960cg pin numbers shown) downloaded from: http:///
ltc1960 11 1960fb test circuit C + C + v ref v sw i th bat1 bat2 chgmon v set 0.5v ea 1960 tc01 ssbsck mosimiso t cyc t dis t ssh t ld t sh t su t h t a t v t ho t sl t lg slave bit 7 out slave bit 0 out bit 0 bit 7 1960 td01 timing diagram spi timing diagram downloaded from: http:///
ltc1960 12 1960fb operation overview the ltc1960 is composed of a battery charger controller, charge mux controller, powerpath controller, spi inter - face, a 10-bit current dac (idac) and 11-bit voltage dac (vdac). when coupled with a low cost microprocessor, it forms a complete battery charger/selector system for two batteries. the battery charger is programmed for voltage and current, and the charging battery is selected via the spi interface. charging can be accomplished only if the voltage at dcdiv indicates that sufficient voltage is avail - able from the input power source, usually an ac adapter. the charge mux, which selects the battery to be charged, is capable of charging both batteries simultaneously by selecting both batteries for charging. the charge mux switch drivers are configured to allow charger current to share between the two batteries and to prevent current from flowing in a reverse direction in the switch. the amount of current that each battery receives will depend upon the relative capacity of each battery and the battery voltage. this can result in significantly shorter charging times (up to 50% for li-ion batteries) than sequential charging of each battery. in order to continue charging, the charge_bat information must be updated more frequently than the internal watchdog timer. the powerpath controller selects which of the pairs of pfet switches, input and output, will provide power to the system load. the selection is accomplished over the spi interface. if the system voltage drops below the threshold set by the lopwr resistor divider, then all of the output side pfets are turned on quickly and power is taken from the highest voltage source available at the dcin, bat1 or bat2 inputs. the input side pfets act as diodes in this mode and power is taken from the source with the highest voltage. the input side powerpath switch driver that is delivering power then closes its input switch to reduce the power dissipation in the pfet bulk diode. in effect, this system provides diode -like behavior from the fet switches, without the attendant high power dissipa - tion from diodes. the microprocessor is informed of this 3-diode mode status when it polls the powerpath status register via the spi interface. the microprocessor can then assess which power source is capable of providing power, and program the powerpath switches accordingly. since high speed powerpath switching at lopwr trip points is handled autonomously, there is no need for real-time microprocessor resources to accomplish this task. simultaneous discharge of both batteries is accomplished by simply programming both batteries for discharge into the system load. the switch drivers prevent reverse current flow in the switches and automatically discharge both bat - teries into the load, sharing current according to the relative capacity of the batteries. simultaneous dual discharge can increase battery operating time by approximately 10% by reducing losses in the switches and reducing internal losses associated with high discharge rates. spi interface the spi interface is used to write to the internal powerpath r egisters, the charger control registers, the current dac, and the voltage dac. the spi is also able to read internal status registers. there are two types of spi write com - mands. the first write command is a 1-byte command used to load powerpath and charger control bits. the second write command is a 2-byte command used to load the dacs. the spi read command is a 2-byte command. in order to ensure the integrity of the spi communication, the last bit received by the spi is echoed back over the miso output after the next falling sck. the data format is set up so that the master has the option of aborting a write if the returned miso bit is not as expected. (refer to block diagram and typical application) downloaded from: http:///
ltc1960 13 1960fb ssbsck mosimiso 1960 f01 byte 1 byte 2 figure 1. spi write to vdac of data = b101_0101_0101 operation 1-byte spi write format: bit 7........byte 1..........bit 0 mosi d0 d1 d2 x a0 a1 a2 0 miso x d0 d1 d2 x a0 a1 a2 charger write address: a[2:0] = b111 charger write data: d2 = x d1 = charge_bat2 d0 = charge_bat1 powerpath write address: a[2:0] = b110 powerpath write data: d2 = power_by_dc d1 = power_by_bat2 d0 = power_by_bat1 2-byte spi write format: bit 7........byte 1..........bit 0 bit 7..........byte 2............bit 0 mosi d0 d1 d2 d3 d4 d5 d6 1 d7 d8 d9 d10 a0 a1 a2 0 miso x d0 d1 d2 d3 d4 d5 d6 1 d7 d8 d9 d10 a0 a1 a2 idac write address: a[2:0] = b000 idac data bits d9-d0: idac value data (msb-lsb) idac data bit d10 : normal mode = 0, low current mode = 1 (dual battery charging is disabled) vdac write address: a[2:0] = b001 vdac data bits d10-d0: vdac value (msb-lsb) subsequent spi communication is inhibited until after the addressed dac is finished loading. it is recommended that the master transmit all zeros until miso goes low. this handshaking procedure is illustrated in figure 1. downloaded from: http:///
ltc1960 14 1960fb ssbsck mosimiso 1960 f02 byte 1 byte 2 figure 2. spi read of fa = 0, lp = 0, dc = 1, pf = 0, and ch = 1 operation 2-byte spi read format: bit 7........byte 1.......bit 0 bit 7........byte 2............bit 0 mosi 0 0 0 0 a0 a1 a2 0 0 0 0 0 a0 a1 a2 1 miso x 0 0 0 0 a0 a1 a2 x fa lp dc pf ch x x status address: a[2:0] = b010 status read data: lp = low_power (low power comparator output) dc = dcdiv (dcdiv comparator output) pf = power_fail (set if selected power supply failed to hold up system power after three tries) ch = charging (one or more batteries are being charged) fa = fault. this bit is set for any of the following conditions: 1) the ltc1960 is still in power-on reset. 2) the ltc1960 has detected a short circuit and has shut down power and charging. 3) the system has asserted a fast off using dcdiv. note: all other values of a[2:0] are reserved and must not be used. a status read is illustrated in figure 2. downloaded from: http:///
ltc1960 15 1960fb battery charger controller the ltc1960 charger controller uses a constant off-time, current mode step-down architecture. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the sr latch and turned off when the main current comparator icmp resets the sr latch. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current reverses, as indicated by current comparator irev, or the beginning of the next cycle. the oscillator uses the equation: t off = 1 f osc ? (v dcin ? v csn ) v dcin to set the bottom mosfet on time. the peak inductor current at which icmp resets the sr latch is controlled by the voltage on i th . i th is in turn controlled by several loops, depending upon the situation at hand. the average current control loop converts the voltage between csp and csn to a representative current. error amp ca2 compares this current against the desired current requested by the idac at the i set pin and adjusts i th until the idac value is satisfied. the bat1/bat2 mux provides the selected battery voltage at chgmon, which is divided down to the v set pin by the vdac resistor divider and is used by error amp ea to decrease i th if the v set voltage is above the 0.8v reference. the amplifier cl1 monitors and limits the input current, normally from the ac adapter, to a preset level (100mv/r cl ). at input current limit, cl1 will decrease the i th voltage and thus reduce battery charging current. an overvoltage comparator, 0v, guards against transient overshoots (>7%). in this case, the top mosfet is turned off until the overvoltage condition is cleared. this feature is useful for batteries which load dump themselves by opening their protection switch to perform functions such as calibration or pulse mode charging. charging is inhibited for battery voltages below the mini - mum charging threshold, v chmin . charging is not inhibited when the low current mode of the idac is selected.the top mosfet driver is powered from a floating boot- strap capacitor c b . this capacitor is normally recharged from v cc through an external diode when the top mosfet is turned off. a 2f to 4.7f capacitor across v cc to gnd is required to provide a low dynamic impedance to charge the boost capacitor. it is also required for stability and power-on reset purposes. as v in decreases towards the selected battery voltage, the converter will attempt to turn on the top mosfet continuously (dropout). a dropout timer detects this condition and forces the top mosfet to turn off, and the bottom mosfet on, for about 200ns at 40s intervals to recharge the bootstrap capacitor. charge mux switches the equivalent circuit of a charge mux switch driver is shown in figure 3. if the charger controller is not enabled, the charge mux drivers will drive the gate and source of the series-connected mosfets to a low voltage and the switch is off. when the charger controller is on, the charge mux driver will keep the mosfets off until the voltage at csn rises at least 35mv above the battery voltage. gch1 is then driven with an error amplifier eac until the volt - age between bat1 and csn satisfies the error amplifier or until gch1 is clamped by the internal zener diode. the time required to close the switch could be quite long (many ms) due to the small currents output by the error amp and depending upon the size of the mosfet switch. if the voltage at csn decreases below v bat1 C 20mv, a comparator cc quickly turns off the mosfets to prevent reverse current from flowing in the switches. in essence, this system performs as a low forward voltage diode. operation is identical for bat2. figure 3. charge mux switch driver equivalent circuit operation C + + C gch1 sch1 q4 q3 to battery 1 from charger bat1 csn 35mv 20mv off dcin + 10v (charge pumped) 10k 1960 f03 eac cc downloaded from: http:///
ltc1960 16 1960fb dual chargingnote that the charge mux switch drivers will operate together to allow both batteries to be charged simultane - ously. if both charge mux switch drivers are enabled, only the battery with the lowest voltage will be charged until its voltage rises to equal the higher voltage battery. the charge current will then share between the batteries according to the capacity of each battery. if both batteries are selected for charging, only batteries with voltages above v chmin are allowed to charge. dual charging is not allowed when the low current mode of the idac is selected. if dual charging is enabled when the idac enters low current mode, then only bat1 will be charged. charger start-up when the charger controller is enabled by the spi i nterface block, the charger output csn will ramp from 0v until it exceeds the selected battery voltage. the clamp error amp is used to prevent the charger output from exceeding the selected battery voltage by more than 0.7v during the start-up transient while the charge mux switches, have yet to close. once the charge mux switches have closed, the clamp releases i th to allow control by another loop. powerpath controllerthe powerpath switches are turned on and off via the spi interface, in any combination. the external p-mosfets are usually connected as an input switch and an output switch. the output switch pfet is connected in series with the input pfet and the positive side of the short-circuit sensing resistor, r sc . the input switch is connected in series between the power source and the output pfet. the powerpath switch driver equivalent circuit is shown in figure 4. the output pfet is driven high and low by the output side driver controlling pin gxxo, the pfet is either on or off. the gate of the input pfet is driven by an error amplifier which monitors the voltage between the input power source (bat1 in this case) and scp. if the switch is turned off, the two outputs are driven to the higher of the two voltages present across the input/output terminals of the switch. when the switch is instructed to turn on, the output side driver immediately drives the gate of the output pfet approximately 6v below the highest of the voltages present at the input/output. when the output pfet turns on, the voltage at scp will be pulled up to a diode drop below the source voltage by the bulk diode of the input pfet. if the source voltage is more than 25mv above scp, eap will drive the gate of the input pfet low until the input pfet turns on and reduces the voltage across the input/output to the eap set point, or until the zener clamp engages to limit the voltage applied to the input pfet. if the source voltage drops more than 20mv below scp, then comparator cp turns on swp to quickly prevent large reverse current in the switch. this operation mimics a diode with a low forward voltage drop. figure 4. powerpath driver equivalent circuit operation C + + C gb1i gb1o q8 q7 from battery 1 bat1 scp 25mv 20mv off off 1960 f04 eap cp swp toload c l r sc autonomous powerpath switching the lopwr comparator monitors the voltage at the load through the resistor divider from pin scn. if any power_by bit is set and the lopwr comparator trips, then all of the switches are turned on (3-diode mode) by the powerpath controller to ensure that the system is powered from the source with the highest voltage. the powerpath controller waits approximately 1 second, to allow power to stabilize, and then reverts to the previous powerpath switch configuration. a power-fail counter is incremented to indicate that a failure has occurred. if the power-fail counter equals a value of 3, then the powerpath controller sets the switches to 3-diode mode and the pf downloaded from: http:///
ltc1960 17 1960fb bit is set in the status register. this is a three-strikes-and- youre-out process which is intended to debounce the powerpath pf indicator. the power-fail counter is reset by a powerpath spi write. short-circuit protection short-circuit protection operates in both a current mode and a voltage mode. if the voltage between scp and scn exceeds the short-circuit comparator threshold v tsc for more than 15ms, then all of the powerpath switches are turned off and the fault bit (fa) is set. similarly, if the voltage at scn falls below 3v for more than 15ms, then all of the powerpath switches are turned off and the fa bit is set. the fa bit is reset by removing all power sources and allowing the voltage at v plus to fall below the uvlo threshold. if the fa bit is set, charging is disabled until v plus exceeds the uvlo threshold and charging is re - quested via the spi interface. when a hard short-circuit occurs, it might pull all of the power sources down to near 0v potentials. the capacitors on v cc and v plus must be large enough to keep the circuit operating correctly during the 15ms short-circuit event. the charger will stop within a few microseconds leaving a small current which must be provided by the capacitor on v plus . the recommended minimum values (1f on v plus and 2f on v cc , including tolerances) should keep the ltc1960 operating above the uvlo trip voltage long enough to perform the short-circuit function when the input voltages are greater than 8v. increasing the capaci - tor across v cc to 4.7f will allow operation down to the recommended 6v minimum. fast powerpath turn-off all of the powerpath switches can be forced off by set - ting the dcdiv pin to a voltage between 8v and 10v. this will have the same effect as a short-circuit event. the pf status bit will also be set. dcdiv must be less than 5v and v plus must decrease below the uvlo threshold to re-enable the powerpath switches. power-up strategy all three powerpath switches are turned on after v plus exceeds the uvlo threshold for more than 250ms. this delay is to prevent oscillation from a turn-on transient near the uvlo threshold. the voltage dac block the voltage dac (vdac) is a delta-sigma modulator which controls the effective value of an internal resistor, r vset = 7.2k, used to program the maximum charger voltage. figure 5 is a simplified diagram of the vdac operation. the charger monitor mux is connected to the appropriate battery indicated by the charge_batx bit. the delta-sigma modulator and switch swv convert the vdac value, received via spi communication, to a vari - able resistance equal to (11/8)r vset /(vdac (value) /2047). in regulation, v set is servo driven to the 0.8v reference voltage, v ref . therefore, programmed voltage is: v batx = (8/11) v ref 405.3k/7.2k ? (vdac (value) /2047) + v ref = 32,752mv ? (vdac (value) /2047) + 0.8v note that the reference voltage must be subtracted from the vdac value in order to obtain the correct output volt - age. this value is v ref /16mv = 50 (32 hex ). capacitors c b1 and c b2 are used to average the voltage present at the v set pin as well as provide a zero in the voltage loop to help stability and transient response time to voltage variations. see the applications information section. operation figure 5. voltage dac operation C + bat2 bat1 c b1 c b2 csn 1960 f05 ea v ref v set r vset 7.2k r vf 405.3k ? modulator swv 11 toi th dac value (11 bits) chgmon downloaded from: http:///
ltc1960 18 1960fb the current dac block the current dac is a delta-sigma modulator which controls the effective value of an internal resistor, r set = 18.77k, used to program the maximum charger current. figure 6 is a simplified diagram of the dac operation. the delta-sigma modulator and switch convert the idac value, received via spi communication, to a variable resistance equal to 1.25r set /(idac (value) /1023). in regulation, i set is servo driven to the 0.8v reference voltage, v ref , and the cur - rent from r set is matched against a current derived from the voltage between pins csp and csn. this current is (v csp C v csn )/3k. therefore, programmed current is: i avg = v ref ? 3k (1 .25r sns r set ) ? idac (value) 1023 ?? ? ?? ? when the low current mode bit (d10) is set to 1, the current dac enters a different mode of operation. the current dac output is pulse-width modulated with a high frequency c lock having a duty cycle value of 1/8. therefore, the maximum output current provided by the charger is i max /8. the delta-sigma output gates this low duty cycle signal on and off. the delta-sigma shift registers are then clocked at a slower rate, about 40ms/bit, so that the charger has time to settle to the i max /8 value. the resulting average charging current is equal to 1/8 of the current programmed in normal mode. dual battery charging is disabled in low current mode. if both batteries are selected for charging, then only bat1 will charge. operation figure 6. current dac operation figure 7. charging current waveform in low current mode C + 1960 f06 v ref i set r set 18.77k ? modulator 10 toi th dac value (10 bits) c set (v csp C v csn ) 3k (from ca1 amplifier) average charger current i max /8 0 ~40ms 1960 f07 downloaded from: http:///
ltc1960 19 1960fb figure 8. adapter current limiting it is actual physical capacity rating at the time of charge. capacity rating will change with age and use and hence the current sharing ratios can change over time. in dual charge mode, the charger uses feedback from the bat2 input to determine charger output voltage. when charging batteries with significantly different initial states of charge (i.e., one almost full, the other almost depleted), the full battery will get a much lower current. this will cause a voltage difference across the charge mux switches, which may cause the bat1 voltage to exceed the programmed voltage. using mosfets in the charge mux with lower r ds(on) will alleviate this problem. adapter limiting an important feature of the ltc1960 is the ability to auto - matically adjust charging current to a level which avoids overloading the wall adapter. this allows the product to operate at the same time that batteries are being charged without complex load management algorithms. addition - ally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. this feature is created by sensing total adapter output cur - rent and adjusting charging current downward if a preset adapter current limit is exceeded. true analog control is used, with closed loop feedback ensuring that adapter load current remains within limits. amplifier cl1 in figure 8 senses the voltage across r cl , connected between the clp and dcin pins. when this voltage exceeds 100mv, the amplifier will override programmed charging current to limit adapter current to 100mv/r cl . a lowpass filter formed by 5k and 0.1f is required to eliminate switch - ing noise. if the current limit is not used, clp should be connected to dcin. 100mv C + 5k clp dcin 11960 f08 0.1f + r cl * c in v in cl1 ac adapter input *r cl = 100mv adapter current limit + applications information automatic current sharing in a dual parallel charge configuration, the ltc1960 does not actually control the current flowing into each individual battery. the capacity, or amp-hour rating, of each battery determines how the charger current is shared. this auto - matic steering of current is what allows both batteries to reach their full capacity points at the same time. in other words, given all other things equal, charge termination will happen simultaneously. a battery can be modeled as a huge capacitor and hence governed by the same laws. i = c ? (dv/dt), where: i = the current flowing through the capacitor c = capacity rating of battery (using amp-hour value instead of capacitance) dv = change in voltage dt = change in time the equivalent model of a set or parallel batteries is a set of parallel capacitors. since they are in parallel, the change in voltage over change in time is the same for both batteries 1 and 2. dv dt bat1 = dv dt bat2 from here we can simplify. i bat1 /c bat1 = dv/dt = i bat2 /c bat2 i bat2 = i bat1 c bat2 /c bat1 at this point you can see that the current divides as the ratio of the two batteries capacity ratings. the sum of the current into both batteries is the same as the current being supply by the charger. this is independent of the mode of the charger (cc or cv). i chrg = i bat1 + i bat2 from here we solve for the actual current for each battery. i bat2 = i chrg c bat2 /(c bat1 + c bat2 ) i bat1 = i chrg c bat1 /(c bat1 + c bat2 ) please note that the actual observed current sharing will vary from manufactures claimed capacity ratings since downloaded from: http:///
ltc1960 20 1960fb watchdog timer charging will begin when either charge_bat1 or charge_bat2 bits are set in the charger register (ad - dress: 111). charging will stop if the charger register is not updated prior to the expiration of the watchdog timer. simply repeating the same data transmission to the charger register at a rate higher than once per second will ensure that charging will continue uninterrupted. extending system to more than two batteries the ltc1960 can be extended to manage systems with more than three sources of power. contact linear technology applications engineering for more information. charging depleted batteries some batteries contain internal protection switches that disconnect a load if the battery voltage falls below what is considered a reasonable minimum. in this case, the charger may not start because the voltage at the battery terminal is less than 5v. the low current mode of the idac must be used in this case to condition the battery. in low current mode, there is no minimum voltage requirement (but dual charging is not allowed). usually, the battery will detect that it is being charged and then close its protec - tion switch, which will allow the idac to switch to normal mode. smart batteries require that charging current not exceed 100ma until valid charging voltage and charging current parameters are transmitted via the smbus. the low current idac mode is ideal for this purpose. starting charge with dissimilar batteries in dual charge mode when charging batteries of different charger termination voltages, the charger should be started using the follow - ing procedure: step 1. select only the lowest termination voltage bat - tery for charging, and set the charger to its charging parameters. step 2. when the battery current is flowing into that bat - tery, change to dual charging mode (without stopping the charger) and set the appropriate charging parameters for this dual charger condition. if this procedure is not followed, and bat2 is significantly higher voltage than bat1, the charger could refuse to charge either battery. charge termination issues batteries with constant-current charging and voltage-based charger termination might experience problems with re - ductions of charger current caused by adapter limiting. it is recommended that input limiting feature be defeated in such cases. consult the battery manufacturer for informa - tion on how your battery terminates charging. setting output current limit the full-scale output current setting of the idac will produce v max = 102.3mv between csp and csn. to set the full- scale current of the dac simply divide v max by r sns . this is expressed by the following equation: r sns = 0.1023/i max table 1. recommended r sns resistor values i max (a) r sns () 1% r sns (w) 1.023 0.100 0.25 2.046 0.050 0.25 4.092 0.025 0.5 8.184 0.012 1 use resistors with low esl.inductor selection higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency gener - ally results in lower efficiency because of mosfet gate charge losses. in addition, the effect of inductor value on ripple current and low current operation must also be considered. the inductor ripple current ?i l decreases with higher frequency and increases with higher v in . ? i l = 1 f ( ) l ( ) v out 1 ? v out v in ?? ? ?? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.4(i max ). in no case should applications information downloaded from: http:///
ltc1960 21 1960fb ?i l exceed 0.6(i max ) due to limits imposed by irev and ca1. remember the maximum ?i l occurs at the maxi - mum input voltage. in practice, 10h is the lowest value recommended for use. charger switching power mosfet and diode selection two external power mosfets must be selected for use with the ltc1960 charger: an n-channel mosfet for the top (main) switch and an n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak gate drive levels are set by the v cc volt - age. this voltage is typically 5.2v. consequently, logic-level threshold mosfets must be used. pay close attention to the b vdss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. the ltc1960 charger is always operating in continuous mode so the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out /v in synchronous switch duty cycle = (v in C v out )/ v in the mosfet power dissipations at maximum output current are given by: p main = v out /v in (i max ) 2 (1 + d ? t )r ds(on) + k(v in ) 2 (i max )(c rss )(f) p sync = (v in C v out )/ v in (i max ) 2 (1 + d ? t ) r ds(on) where d ? t is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v, the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. the term (1 + d ? t ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/c can be used as an approximation for low voltage mosfets. c rss is usu - ally specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. if the ltc1960 charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the top - side n-channel efficiency generally improves with a larger mosfet. using asymmetrical mosfets may achieve cost savings or efficiency gains. the schottky diode d1, shown in the typical application on the back page, conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 1a schottky is generally a good size for 4a regulators due to the relatively small average current. larger diodes can result in additional transition losses due to their larger junction capacitance. the diode may be omitted if the efficiency loss can be tolerated. calculating ic power dissipation the power dissipation of the ltc1960 is dependent upon the gate charge of q tg and q bg (refer to typical application). the gate charge is determined from the manufacturers data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the fet. p d = (v dcin C v vcc ) ? [f osc (q tg + q bg ) + i vcc ] + v dcin ? i dcin example: v vcc = 5.2v, v dcin = 19v, f osc = 345khz, q g2 = q g3 = 15nc, i vcc = 0ma. p d = 165mw applications information downloaded from: http:///
ltc1960 22 1960fb v set /i set capacitors capacitor c7 is used to filter the delta-sigma modulation frequency components to a level which is essentially dc. acceptable voltage ripple at i set is about 10mv p-p . since the period of the delta-sigma switch closure, t ? , is about 10s and the internal idac resistor, r set , is 18.77k, the ripple voltage can be approximated by: ? v iset = v ref ? t ? r set ? c7 then the equation to extract c7 is: c7 = v ref ? t ? ? v iset ? r set = 0.8/0.01/18.77k(10s) @ 0.043f in order to prevent overshoot during start-up transients, the time constant associated with c7 must be shorter than the time constant of c5 at the i th pin. if c7 is increased to improve ripple rejection, then c5 should be increased proportionally and charger response time to average cur - rent variation will degrade.capacitor c b1 and c b2 are used to filter the vdac delta- sigma modulation frequency components to a level which is essentially dc. c b2 is the primary filter capacitor and c b1 is used to provide a zero in the response to cancel the pole associated with c b2 . acceptable voltage ripple at v set is about 10mv p-p . since the period of the delta- sigma switch closure, t ? , is about 11s and the internal vdac resistor, r vset , is 7.2k, the ripple voltage can be approximated by: ? v vset = v ref ? t ? r vset c b1 || c b2 ( ) then the equation to extract c b1 || c b2 is: c b1 || c b2 = v ref ? t ? r vset ? v vset c b2 should be 10 to 20 c b1 to divide the ripple voltage present at the charger output. therefore c b1 = 0.01f and c b2 = 0.1f are good starting values. in order to prevent overshoot during start-up transients the time constant as - sociated with c b2 must be shorter than the time constant of c5 at the i th pin. if c b2 is increased to improve ripple rejection, then c5 should be increased proportionally and charger response time to voltage variation will degrade. input and output capacitors in the 4a lithium battery charger (typical application section), the input capacitor (c in ) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. worst-case rms ripple current will be equal to one-half of output charging current. actual capacitance value is not critical. solid tantalum, low esr capacitors have a high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass. high input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. solid tantalum capaci - tors have a known failure mechanism when subjected to very high turn-on surge currents. only kemet t495 series of surge robust low esr tantalums are rated for high surge conditions such as battery to ground. the relatively high esr of an aluminum electrolytic for c15, located at the ac adapter input terminal, is helpful in reducing ringing during the hot-plug event. highest possible voltage rating on the capacitor will minimize problems. consult with the manufacturer before use. alternatives include new high capacity ceramic (at least 20f) from tokin, united chemi-con/marcon, et al. other alternative capacitors include oscon capacitors from sanyo. the output capacitor (c out ) is also assumed to absorb output switching current ripple. the general formula for capacitor current is: i rms = 0 .29(v bat ) 1 ? v bat v dcin ?? ? ?? ? (l1)(f) for example:v dcin = 19v, v bat = 12.6v, l1 = 10h, and f = 300khz, i rms = 0.41a. applications information downloaded from: http:///
ltc1960 23 1960fb emi considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300khz switching frequency. switching ripple current splits be - tween the battery and the output capacitor depending on the esr of the output capacitor and the battery impedance. if the esr of c out is 0.2 and the battery impedance is raised to 4 with a bead or inductor, only 5% of the cur - rent ripple will flow in the battery. powerpath and charge mux mosfet selection three pairs of p-channel mosfets must be used with the wall adapter and the two battery discharge paths. two pairs of n-channel mosfets must be used with the battery charge path. the nominal gate drive levels are set by the clamp drive voltage of their respective control circuitry. this voltage is typically 6.25v. consequently, logic-level threshold mosfets must be used. pay close attention to the b vdss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , input voltage and maximum out- put current. for the n-channel charge path, the maximum current is the maximum programmed current to be used. for the p-channel discharge path maximum current typi - cally occurs at end of life of the battery when using only one battery. the upper limit of r ds(on) value is a function of the actual power dissipation capability of a given mosfet package that must take into account the pcb layout. as a starting point, without knowing what the pcb dissipation capability would be, derate the package power rating by a factor of two. r ds(on)max = p mosfet 2 i max ( ) 2 if you are using a dual mosfet package with both mos - fets in series, you must cut the package power rating in half again and recalculate. r ds(on)max = p mosfetdual 4 i max ( ) 2 if you use identical mosfets for both battery paths, voltage drops will track over a wide current range. the ltc1960 linear 25mv cv drop regulation will not occur until the current has dropped below: i linearmax = 25mv 2 r ds(on)max however, if you try to use the above equation to determine r ds(on) to force linear mode at full current, the mosfet r ds(on) value becomes unreasonably low for mosfets available at this time. the need for the ltc1960 voltage drop regulation only comes into play for parallel battery configurations that terminate charge or discharge using voltage. at first this seems to be a problem, but there are several factors helping out: 1. when batteries are in parallel current sharing, the cur rent flow through any one battery is less than if it is running standalone. 2. most batteries that charge in constant-voltage mode, such as li-ion, charge terminate at a current value of c/10 or less which is well within the linear operation range of the mosfets. 3. voltage tracking for the discharge process does not need such precise voltage tracking values. the ltc1960 has two transient conditions that force the discharge path p-channel mosfets to have two additional parameters to consider. the parameters are gate charge q gate and single pulse power capability. when the ltc1960 senses a low_power event, all the p-channel mosfets are turned on simultaneously to allow voltage recovery due to a loss of a given power source. however, there is a delay in the time it takes to turn on all the mosfets. slow mosfets will require more bulk capacitance to hold up all the systems power sup - ply function during the transition and fast mosfet will require less bulk capacitance. the transition speed of a mosfet to an on or off state is a direct function of the mosfet gate charge. t = q gate i drive applications information downloaded from: http:///
ltc1960 24 1960fb i drive is the fixed drive current into the gate from the ltc1960 and t is the time it takes to move that charge to a new state and change the mosfet conduction mode. hence, time is directly related to q gate . since q gate goes up with mosfets of lower r ds(on) , choosing such mosfets has a counterproductive increase in gate charge making the mosfet slower. please note that the ltc1960 recovery time specification only refers to the time it takes for the voltage to recover to the level just prior to the low_power event as opposed to full voltage. the single pulse current rating of the mosfet is important when a short-circuit takes place. the mosfet must survive a 15ms overload. mosfets of lower r ds(on) or mosfets that use more powerful thermal packages will have a high power surge rating. using too small of a pulse rating will allow the mosfet to blow to the open-circuit condition instantly like a fuse. typically there is no outward sign of failure because it happens so fast. please measure the surge current for all discharge power paths under worse case conditions and consult the mosfet data sheet for the limitations. voltage sources with the highest voltage and the most bulk capacitance are often the biggest risk. specifically the mosfets in the wall adapter path with wall adapters of high voltage, large bulk capacitance and low resistance dc cables between the adapter and device are the most common failures. remember to only use the real wall adapter with a production dc power cord when per - forming the wall adapter path test. the use of a laboratory power supply is unrealistic for this test and will force you to over specify the mosfet ratings. a battery pack usu - ally has enough series resistance to limit the peak current or are too low in voltage to create enough instantaneous power to damage their respective powerpath mosfets. pcb layout considerations for maximum efficiency, the switch node rise and fall time is kept as short as possible. to prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the ic is essential. 1. keep the highest frequency loop path as small and tight as possible. this includes the bypass capacitors, with the higher frequency capacitors being closer to the noise source than the lower frequency capacitors. the highest frequency switching loop has the highest layout priority. for best results, avoid using vias in this loop and keep the entire high frequency loop on a single external pcb layer. if you must, use multiple vias to keep the impedance down (see figure 9). applications information figure 10. kelvin sensing of charging current figure 9. high speed switching path 1960 f09 v bat l1 v in high frequency circulating path bat switch node c in c out d1 csp 1960 f10 direction of charging current r sns csn 2. run long power traces in parallel. best results are achieved if you run each trace on separate pcb layer one on top of the other for maximum capacitance coupling and common mode noise rejection. 3. if possible, use a ground plane under the switcher circuitry to minimize capacitive interplane noise cou - pling. 4. keep signal or analog ground separate. tie this analog ground back to the power supply at the output ground using a single point connection. 5. for best current programming accuracy provide a kelvin connection from r sense to csp and csn. see figure 10 as an example. downloaded from: http:///
ltc1960 25 1960fb package description g36 ssop 0204 0.09 ? 0.25 (.0035 ? .010) 0 ? 8 0.55 ? 0.95 (.022 ? .037) 5.00 ? 5.60** (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 123 4 5 6 7 89 10 11 12 14 15 16 17 18 13 12.50 ? 13.10* (.492 ? .516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ? 0.38 (.009 ? .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout 1.25 0.12 g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) downloaded from: http:///
ltc1960 26 1960fb 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) 37 12 38 bottom viewexposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 packageoutline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notchr = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) package description downloaded from: http:///
ltc1960 27 1960fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 04/11 updated absolute maximum ratings section added note 8updated pin functions updated equation in the current dac block section updated equation in calculating ic power dissipation section updated typical application 25 8, 9 1821 28 (revision history begins at rev b) downloaded from: http:///
ltc1960 28 1960fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2001 lt 0411 rev b ? printed in usa related parts typical application part number description comments lt1505 high efficiency battery charger up to 97% efficiency; ac adapter current limit ltc1628-pg 2-phase, dual synchronous step-down controller minimizes c in and c out ; power good output; 3.5v v in 36v ltc1709 2-phase, dual synchronous step-down controller with vid up to 42a output; minimum c in and c out ; uses smallest components for intel and amd processors ltc3711 no r sense ? synchronous step-down controller with vid 3.5v v in 36v; 0.925v v out 2v; for transmeta, amd and intel mobile processors ltc1759 smbus controlled smart battery charger synchronous operation for high efficiency; integrated smbus accelerator; ac adapter current limit lt1769 2a battery charger constant-current/constant-voltage switching regulator; input current limiting maximizes charge current 2429 32 2019 21 18 17 25 35 36 34 33 13 28 16 cb1 0.01f cb2 0.1f c3 0.01f r6 100 r749.9k 1% r51k 1% r4 14k 1% c50.15f cl20f 25v c7 0.1f r9 3.3k 1% d2 17 6 9 8 11 10 5 4 12 22 23 14 15 30 31 32 27 26 c4 0.1f qbg qtg l1 10h 4a r sns 0.025 1% c in 20f25v c out 20f 25v clpdcin bat1 bat2 miso sck mosi ssb dcdiv comp1 gch2 sch2 gch1 sch1 vset vcc gnd ltc1960 vplus gdci gdco gb1i gb1o gb2i gb2o scp scn lopwr csn csp ith iset sw boost tgate bgate pgnd r15.1k 1% r2649k 1% r3 100k 1% r cl 0.03 r sc 0.02 ssb bat2 bat1 v in sck mosi miso c1 0.1f c2 1f q1q2 q6q5 q7q8 q4 q3 1960 ta02 load q9 q10 c9100pf c6 1f q1, q2, q5, q6, q7, q8: si4925dyq3, q4, q9, q10, qtg, qbg: fds6912a d1: mbr130t3 d2: cmdsh-3 type d3, d4: bat54a type powerpath mux charge mux v dd 4.7k d1 100 c8 0.1f r111k bat2 bat1 d4 d3 c62f dual battery selector and 4a charger (ltc1960cg pin numbers shown) downloaded from: http:///

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